For high power applications, e.g. for powering large microprocessors that operate at 2V and sink approximately 50 A, single semiconductor devices are typically inadequate to provide the requisite power. Power transistors in the form of arrays of transistors are commonly used. These comprise arrays of transistors connected in parallel. FIG. 1 shows a plan view of a typical rectangular array 100 of NMOS devices. Each polygate 102 supports a plurality of drains and sources (not shown) to define a plurality of NMOS transistors. For each polygage, the drains and sources are typically arranged as opposed, staggered, comb-like structures to define alternating drains and sources extending along both sides of the polygate for the width of the polygate 100.
Array structures are also formed from other devices such as LDMOS, but due to the octagonal configuration of LDMOS devices, such arrays typically have a honeycomb-like layout.